The present invention relates in general to fabrication methods and resulting structures for transistors formed in integrated circuits (ICs). More specifically, the present invention relates to improved systems, fabrication methods and resulting structures for vertical field effect transistors (FET) that reduce unwanted capacitance caused by excessive overlap between the gate region and the source/drain regions.
Semiconductor devices are typically formed in active regions of a wafer. In an IC having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in the active region of the semiconductor wafer or substrate by implanting n-type or p-type impurities therein. A MOSFET can be considered a planar device because its channel extends laterally with respect to the major surface of the device substrate. Thus, current flows laterally through the planar MOSFET channel. One type of non-planar MOSFET is known generally as a vertical FET. In order to decrease gate pitch (i.e., the center-to-center distance between adjacent gate structures) and increase device density on the wafer, the channel region of a vertical FET is substantially perpendicular with respect to the major surface of the device substrate. Thus, current flows vertically through the non-planar vertical FET channel.